1. Field of the Invention
The present invention relates to capacitive structure in general and, more particularly, to providing such structure on a VLSI chip using CMOS technology.
2. Prior Art
VLSI (Very Large Scale Integration) technology has progressed to the point where it is now possible to fabricate entire electrical systems on a single silicon chip. Usually, such silicon chips are dominated by digital components such as logic and memory circuits. However, some predominately digital chips do have between one and five percent of the chip area as analog devices. The capacitor is one of the analog devices which is usually needed on the predominantly digital chip.
Since the VLSI chip is dominated by digital devices, the process is optimized around digital circuits even though it is desirable to have a fabricating process that is equally effective in manufacturing both analog and digital circuits. Even though the CMOS process is optimized around digital circuits, it is believed that the CMOS process comes closest to meeting the requirements for effectively manufacturing both digital and analog components. Stated another way, the CMOS process is extremely efficient in laying down digital components on a mixed circuit chip (i.e., a chip carrying both analog and digital circuits). It is less efficient in laying down analog circuits. However, it is more efficient in laying down analog circuits than any of the known fabricating processes where the ultimate goal is VLSI logic mixed with analog.
The use of a modified CMOS process for fabricating capacitors is well documented in the prior art. A modified CMOS process is one in which additional process steps are added in order to fabricate the analog components on the chip. Examples of modified CMOS processes are set forth in the following articles: Hodges, D., et al, "Potential of MOS Technologies for Analog Integrated Circuits," IEEE ISSC, June 1978, pp. 285-294; Ham, P., and Newman, D., "Digital CMOS Cell Library Adopts Analog Circuits," Electronic Design, Dec. 8, 1983, pp. 107-114, and Stone, D, et al, "Analog Building Blocks for Custom and Semi-custom Applications," IEEE ISSC, February 1984, p. 55.
In DS1639-451, U.S. Pat. No. 4,214,252, U.S. Pat. No. 4,005,466 and JP 56-153778, voltage independent capacitors have been formed by using extra process steps to generate a conductive layer under the gate oxide.
Even though the use of additional process steps is a move in the right direction, the additional process steps add cost and complexity to the final chip.
In addition, voltage dependent capacitors have been formed from PN junction devices reversed bias to form varactors. Prior art examples of this technique are given in U.S. Pats. Nos. 4,003,004; 4,143,383; 3,909,637; 3,586,929; 3,582,823; 3,569,865; 3,559,104; 3,290,618; 3,139,596 and 3,109,995. The problem with this approach is that the varactor capacitance changes with reverse voltage. Thus, as the voltage across the varactor changes the capacitance also change. Also, some of the varactors have to be biased with inductors which cannot be integrated on a chip.